Samsung S3C2500B User Manual page 271

S3C2500B
HCLKO
nRCS
nSDWE
ALE
DATA
tADDRd
tGCSd
tCOS
tALEd tnSDWEd
tALEh
tMA
Addr
tADDRh
TACC = 0x4 (4 cycles)
TCOH = 0x1 (1 cycle)
MBE = 1 (Enable)
Figure 5-20. Write Timing Diagram (Muxed Bus)
tACC
tDATAd
Data
TCOS = 0x1 (1 cycle)
TMA = 0x2 (2 cycles)
MEMORY CONTROLLER
tGCSh
tCOH
tnSDWEh
tDATAh
Data Fetch
5-35