Samsung S3C2500B User Manual page 244

MEMORY CONTROLLER
Table 5-5 and 5-6.
Using big-endian and half-word access, Program/Data path between register and external memory.
WA=Address whose LSB is 0, 4, 8, C, EA=External Address
HA=Address whose LSB is 0, 2, 4, 6, 8, A, C, E
BA=Address whose LSB is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
X=Don't care.
Table 5-5. External 16-bit Datawidth Store Operation with Big-Endian
Transfer Width
Bit Num.
CPU Register Data
CPU Address
Bit Num.
CPU Data Bus
External Address (ADDR)
Bit Num.
External Data
Timing Sequence
Table 5-6. External 16-bit Datawidth Load Operation with Big-Endian
Transfer Width
Bit Num.
CPU Register Data
CPU Address
Bit Num.
CPU Data Bus
External Address (ADDR)
Bit Num.
External Data
Timing Sequence
5-8
STORE (CPU Reg → → External Memory)
32-bit
31 0
abcd
WA
31 0
abcd
EA EA+1
15 0 15 0
ba dc
1st 2nd
LOAD (CPU Reg ← ← External Memory)
32-bit
31 0
abcd
WA
31 0 31 0
abxx abcd
EA EA + 1
15 0 15 0
ba dc
1st 2nd
16-bit
31 0 31 0
xxab xxxa
HA BA
31 0 31 0
abab aaaa
EA
15 0 15 0
ba xa
16-bit
31 0 31 0
xxab xxxa
HA BA
31 0 31 0
abab aaaa
EA
15 0
ba
S3C2500B
8-bit
31 0
xxxb
BA+1
31 0
bbbb
EA
15 0
bx
8-bit
31 0
xxxb
BA+1
31 0
bbbb
EA
15 0
ba