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S3C2500B
31
19
18 17 16
T
H
E
I
E
[0] Receive Data Valid Interrupt Enable (RDVIE)
[1] Break Signal Detected Interrupt Enable (BKDIE)
[2] Frame Error Interrupt Enable (FERIE)
[3] Parity Error Interrupt Enable (PERIE)
[4] Overrun Error Interrupt Enable (OERIE)
[5] Control Character Detect Interrupt Enable (CCDIE)
[6] Data Carrier Detect Lost Interrupt Enable (DCDLIE)
[7] Receive FIFO Data Trigger Level Reach Interrupt Enable (RFREAIE)
[9:8] Reserved
[10] Receive FIFO overrun Interrupt Enable (OVFFIE)
[11] Reserved
[12] Receive Event Time out Interrupt Enable (E_RxTOIE)
[13] AutoBaud Rate Detection done interrupt enable (AUBDDNIE)
[15:14] Reserved
[16] CTS event occured Interrupt Enable (E_CTSIE)
[17] Transmitter Idle (TIIE)
[18] Transmit Holding Register Empty Interrupt Enable (THEIE)
This bit used in FIFO mode for interrupt enable when transmit
FIFO empty as much transmit data trigger level.
[31:19] Reserved
Figure 14-4. High-Speed UART Interrupt Enable Register
15
14
13 12 11
10 9
T
E
A
E
O
I
_
U
_
V
I
C
B
R
F
E
T
D
X
F
S
D
T
I
I
N
O
E
E
I
I
E
E
SERIAL I/O (HIGH-SPEED UART)
8 7 6
5
4
3
2
1
R
D
C
O
P
F
B
F
C
C
E
E
E
K
R
D
D
R
R
R
D
E
L
I
I
I
I
I
A
I
E
E
E
E
E
I
E
E
0
R
D
V
I
E
14-15
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