Samsung S3C2500B User Manual page 326

ETHERNET CONTROLLER
7.4.1.2 Buffered DMA Receive Control Register
Register Address
BDMARXCONA 0xF00A0004
BDMARXCONB 0xF00C0004
Bit Number
[3:0] BDMA Rx Number of
Buffer
Descriptor (BRxNBD)
[5:4] BDMA Rx word alignment
(BRxWA)
[6] Reserved
[7] Rx Byte Swapping
(BRxBSWAP)
[8] Reserved
[9]
[10] BDMA Rx enable (BRxEn)
[11] BDMA Rx reset (BRxRS)
[31:12] Reserved
7-16
Table 7-6. BDMA RXCON Register
R/W
R/W
R/W
Table 7-7. BDMA Receive Control Register Description
Bit Name
You can select number of buffer descriptor.
0000 = 2
The Rx word alignment bits determine how many bytes are
invalid in the first word of each data frame. These invalid bytes
are inserted when the word is assembled by the BDMA.
'00' = No invalid bytes, '01' = 1 invalid byte,
'10' = 2 invalid bytes, and '11' = 3 invalid bytes.
Not applicable.
Use to prevent disorder of byte sequence when memory operate
on big-endian format and byte unit access.
If this bit is set, the reception byte is swapped.
(B3,B2,B1,B0) -> (B0,B1,B2,B3)
Not applicable.
– Factorial test bits
When the Rx enable bit is set to '1', the BDMA Rx block is
enabled. Even if this bit is disabled, buffer data will be moved to
the BDMA RxBUFF until the MAC RxFIFO underflows.
This bit is automatically disabled when the BDMA is not the
owner.
NOTE:
Set this bit to '1' to reset the BDMA Rx block.
Description
Buffered DMA receive control register
Buffered DMA receive control register
Description
0 1
, 0001 = 2 , 0010 = 2
The buffer descriptor start address pointer must be
assigned before this bit is set.
Rest Value
0x00000000
0x00000000
2 12
,....., 11xx = 2
S3C2500B