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S3C2500B
31
28
27
Cond
Figure 3-17. Half-word and Signed Data Transfer with Immediate Offset and Auto-Indexing
3.10.1 OFFSETS AND AUTO-INDEXING
The offset from the base may be either a 8-bit unsigned binary immediate value in the instruction, or a second
register. The 8-bit offset is formed by concatenating bits 11 to 8 and bits 3 to 0 of the instruction word, such that
bit 11 becomes the MSB and bit 0 becomes the LSB. The offset may be added to (U = 1) or subtracted from (U =
0) the base register Rn. The offset modification may be performed either before (pre-indexed, P = 1) or after
(post-indexed, P = 0) the base register is used as the transfer address.
The W bit gives optional auto-increment and decrement addressing modes. The modified base value may be
written back into the base (W = 1), or the old base may be kept (W = 0). In the case of post-indexed addressing,
the write back bit is redundant and is always set to zero, since the old base value can be retained if necessary by
setting the offset to zero. Therefore post-indexed data transfers always write back the modified base.
The Write-back bit should not be set high (W = 1) when post-indexed addressing is selected.
25
24
23
22
21
20
19
000
P U
1
W
L
[3:0] Immediate Offset (Low Nibble)
[6][5] S H
0 0 = SWP instruction
0 1 = Unsigned halfwords
1 1 = Signed byte
1 1 = Signed half words
[11:8] Immediate Offset (High Nibble)
[15:12] Source/Destination Register
[19:16] Base Register
[20] Load/Store
0 = Store to memory
1 = Load from memory
[21] Write-back
0 = No write-back
1 = Write address into base
[23] Up/Down
0 = Down: subtract offset from base
1 = Up: add offset to base
[24] Pre/Post Indexing
0 = Post: add/subtract offset after transfer
1 = Pre: add/subtract offset bofore transfer
[31:28] Condition Field
16
15
12
11
Rn
Rd
Offset
INSTRUCTION SET
8 7 6 5 4 3
1
S H 1
Offset
0
3-35
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