Dma Rx Buffer Descriptor Pointer Register; Maximum Frame Length Register - Samsung S3C2500B User Manual

HDLC CONTROLLER

8.7.12 DMA RX BUFFER DESCRIPTOR POINTER REGISTER

The DMA receive buffer descriptor pointer register contains the address of the Rx buffer data pointer on the data
to be received. During a DMA operation, the buffer descriptor pointer is updated by the next buffer data pointer.
Registers
0×F010003C
HDMARXPTRA
0×F011003C
HDMARXPTRB
0×F012003C
HDMARXPTRC
31 30 29 28 27

8.7.13 MAXIMUM FRAME LENGTH REGISTER

The HDLC controller checks the length of an incoming frame against the user-defined value in DMA mode. If the
frame received exceeds this register value, the frame is discarded, and FLV(Frame Length Violated) bit is set in
the buffer descriptor belonging to that frame.
Registers
0×F0100040
HMFLRA
0×F0110040
HMFLRB
0×F0120040
HMFLRC
31 30 29 28 27
8-50
Table 8-20. DMA Rx Buffer Descriptor Pointer Registers
Address R/W
R/W
R/W
R/W
26 25
[25:0] DMA Rx buffer descriptor pointer
Figure 8-24. DMA Rx Buffer Descriptor Pointer
Table 8-21. HDMATXCNT and HDMARXCNT Registers
Address R/W
R/W
R/W
R/W
26 25 24 23 22 21 20 19
[15:0] Maximum frame length
Figure 8-25. Maximum Frame Length Register
Description
DMA Rx Buffer Descriptor Pointer
DMA Rx Buffer Descriptor Pointer
DMA Rx Buffer Descriptor Pointer
DMA Rx Buffer Descriptor Pointer
Description
Maximum Frame Length
Maximum Frame Length
Maximum Frame Length
18 17 16 15
Maximum Frame Length
S3C2500B
Reset Value
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0
Reset Value
0xXXXX0000
0xXXXX0000
0xXXXX0000
0