Gdma Special Registers - Samsung S3C2500B User Manual

S3C2500B

12.3 GDMA SPECIAL REGISTERS

Registers Address
DPRIC 0xF0051000
DPRIF 0xF0052000
DPRIR 0xF0053000
DCON0 0xF0050000
DSAR0 0xF0050004
DDAR0 0xF0050008
DTCR0 0xF005000C
DRER0 0xF0050010
DIPR0 0xF0050014
DCON1 0xF0050020
DSAR1 0xF0050024
DDAR1 0xF0050028
DTCR1 0xF005002C
DRER1 0xF0050030
DIPR1 0xF0050034
DCON2 0xF0050040
DSAR2 0xF0050044
DDAR2 0xF0050048
DTCR2 0xF005004C
DRER2 0xF0050050
DIPR2 0xF0050054
DCON3 0xF0050060
DSAR3 0xF0050064
DDAR3 0xF0050068
DTCR3 0xF005006C
DRER3 0xF0050070
DIPR3 0xF0050074
DCON4 0xF0050080
DSAR4 0xF0050084
DDAR4 0xF0050088
DTCR4 0xF005008C
DRER4 0xF0050090
DIPR4 0xF0050094
DCON5 0xF00500A0
DSAR5 0xF00500A4
DDAR5 0xF00500A8
DTCR5 0xF00500AC
DRER5 0xF00500B0
DIPR5 0xF00500B4
Table 12-1. GDMA Special Registers Overview
R/W
R/W GDMA priority configuration register
R/W GDMA programmable priority register for fixed
R/W GDMA programmable priority register for round-robin
R/W GDMA channel 0 control register
R/W GDMA channel 0 source address register
R/W GDMA channel 0 destination address register
R/W GDMA channel 0 transfer count register
W GDMA channel 0 run enable register
R/WC GDMA channel 0 interrupt pending register
R/W GDMA channel 1 control register
R/W GDMA channel 1 source address register
R/W GDMA channel 1 destination address register
R/W GDMA channel 1 transfer count register
W GDMA channel 1 run enable register
R/WC GDMA channel 1 interrupt pending register
R/W GDMA channel 2 control register
R/W GDMA channel 2 source address register
R/W GDMA channel 2 destination address register
R/W GDMA channel 2 transfer count register
W GDMA channel 2 run enable register
R/WC GDMA channel 2 interrupt pending register
R/W GDMA channel 3 control register
R/W GDMA channel 3 source address register
R/W GDMA channel 3 destination address register
R/W GDMA channel 3 transfer count register
W GDMA channel 3 run enable register
R/WC GDMA channel 3 interrupt pending register
R/W GDMA channel 4 control register
R/W GDMA channel 4 source address register
R/W GDMA channel 4 destination address register
R/W GDMA channel 4 transfer count register
W GDMA channel 4 run enable register
R/WC GDMA channel 4 interrupt pending register
R/W GDMA channel 5 control register
R/W GDMA channel 5 source address register
R/W GDMA channel 5 destination address register
R/W GDMA channel 5 transfer count register
W GDMA channel 5 run enable register
R/WC GDMA channel 5 interrupt pending register
Description
GDMA CONTROLLER
Reset Value
×
0 00000000
0x00543210
0x00000000
×
0 00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
×
0 00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
×
0 00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
×
0 00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
×
0 00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
×
0 00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
12-3