Samsung S3C2500B User Manual page 319

S3C2500B ETHERNET CONTROLLER
7.3.7.3 Buffer Descriptor
The ownership bit in the buffer descriptor controls the owner of the descriptor. When the ownership bit is '1', the
BDMA controller owns the descriptor. When the bit is '0', the CPU owns the descriptor. The owner of the
descriptor always owns the associated data frame. (The descriptor's frame start address field always points to
this frame.)
Software sets the BDMARXLEN register to the length, and also sets the BDMARXDPTR register to point to a
chain of buffer descriptors, all of which have their ownership bits set.
The BDMA engine can then be started to set the BDMARXCON.10 (BRxEn). When a frame is received, it is
copied into the external memory at the address specified by the BDMARXDPTR register. Please note that no
configurable offset or page boundary calculation is required. The received frame is written into the buffer in the
external memory until the end of frame is reached, or until the length exceeds the configured maximum frame
size. If the entire frame is received successfully, the status bits in the buffer descriptor are set to indicate this.
Otherwise, the status bits are set to indicate that an error occurred. The ownership bit in the status and length
field is cleared and an interrupt may now be generated. The length field in the Rx buffer descriptor is updated in
summation with previous length filed of Rx buffer descriptor. The BDMA points the next buffer descriptor
automatically, but BDMATXDPTR and BDMARXDPTR is not updated to the next pointer. It always has the first
buffer descriptor address. Because BDMA pointers are fixed as initial addresses, BDMA count register values
indicate the number of frames to be handled by BDMA.
In addition, users can determine how many buffer descriptors to use by controlling the BDMATXCON.3~0
(BTxNBD) and BDMARXCON.3-0 (BRxNBD). If the last buffer descriptor was used by the BDMA, the next buffer
is the first buffer and BDMA count register value goes to zero. Finally, the status and length fields in the first and
the last Rx buffer descriptors are updated. The length field value is same in the first and last Rx buffer descriptor.
The status field of the middle Rx buffer descriptors does not have any mean.
When the received frame size exceeds the maximum frame size (BRxMFS bits of BDMARXLEN), the data
frame will be overwritten by the last word of maximum frame. If overflow occurred, this status is written to status
field bit.20 in the Rx buffer descriptor. When the BDMA reads a descriptor, if the ownership bit is not set, it has
two options:
— Skip to the next buffer descriptor, or
— Generate an interrupt and halt the BDMA operation. If CPU set to skip bit in Rx buffer descriptor's status
field, BDMA goes next buffer without interrupt or BDMA stop.
During transmission, the two-byte frame length at the Tx buffer descriptor is moved into the BDMA internal Tx
counter. After transmission, Tx status is saved in the Tx buffer descriptor. The BDMA points to the next buffer
descriptor address register for the linked list structure. However, BDMATXDPTR register cannot be updated.
You should check BTXBDCNT register to detect how many frames were handled.
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