Register Page Pointer (Pp) - Samsung S3C80A5B User Manual

S3C80A5B

REGISTER PAGE POINTER (PP)

The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using an
8-bit data bus) into as many as 15 separately addressable register pages. Page addressing is controlled by the
register page pointer (PP, DFH). In the S3C80A5B microcontroller, a paged register file expansion is not
implemented and the register page pointer settings therefore always point to "page 0."
Following a reset, the page pointer's source value (lower nibble) and destination value (upper nibble) are always
'0000', automatically selecting page 0 as the source and destination page for register addressing. These page
pointer (PP) register settings, as shown in Figure 2-3, should not be modified during normal operation.
Dectination register page selection bits:
0 0 0 0
NOTE: In the S3C80A5B microcontroller, only pate 0 is implemented.
Register Page Pointer (PP)
MSB .7 .6 .5
Destination: page 0
A hardware reset operation writes the 4-bit destination and source values
shown above to the register pate pointer. These values should not be
modified.
Figure 2-3. Register Page Pointer (PP)
DFH, Set 1, R/W
.4 .3 .2
Source register page selection bits:
0 0 0 0
.1 .0 LSB
Source: page 0
ADDRESS SPACES
2-5