STMicroelectronics STM32F405 Reference Manual page 1232

Ethernet (ETH): media access control (MAC) with DMA controller
Table 194. Ethernet register map and reset values (continued)
Offset Register
ETH_PTPTSSR
0x728
Reset value
ETH_PTPPPSC
R
0x72C
Reset value
ETH_DMABMR
0x1000
Reset value
ETH_DMATPDR
0x1004
Reset value 0
ETH_DMARPDR
0x1008
Reset value 0
ETH_DMARDLA
R
0x100C
Reset value 0
ETH_DMATDLA
R
0x1010
Reset value 0
ETH_DMASR
0x1014
Reset value
ETH_DMAOMR
0x1018
Reset value
ETH_DMAIER
0x101C
Reset value
ETH_DMAMFB
Reserve
OCR
0x1020
Reset value
ETH_
DMARSWTR
0x1024
Reset value
ETH_
DMACHTDR
0x1048
Reset value 0
ETH_
DMACHRDR
0x104C
Reset value 0
ETH_
DMACHTBAR
0x1050
Reset value 0
ETH_
DMACHRBAR
0x1054
Reset value 0
Refer to Section: Memory map for the register boundary addresses.
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Reserved
0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0
Reserved
0 0 0
Reserved
d
0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
DocID018909 Rev 11
Reserved
Reserved
RDP PM
0 0 0 0 0 1 0 0 0
TPD
0 0 0 0 0 0 0 0 0
RPD
0 0 0 0 0 0 0 0 0
SRL
0 0 0 0 0 0 0 0 0
STL
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
Reserve
d
0 0 0 0 0
0 0 0
0 0 0 0 0 0 0 0 0
Reserved
HTDAP
0 0 0 0 0 0 0 0 0
HRDAP
0 0 0 0 0 0 0 0 0
HTBAP
0 0 0 0 0 0 0 0 0
HRBAP
0 0 0 0 0 0 0 0 0
PBL
0 0 0 0 0 1 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0
Reserved
0 0 0
0 0 0 0 0 0
MFC
0 0 0 0 0 0 0 0
0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
RM0090
0 0
PPS
FREQ
0 0 0
DSL
0 0 0 0 0 1
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
RSWTC
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0