STMicroelectronics STM32F405 Reference Manual page 1404

USB on-the-go high-speed (OTG_HS)
OTG_HS core interrupt register (OTG_HS_GINTSTS)
Address offset: 0x014
Reset value: 0x0400 0020
This register interrupts the application for system-level events in the current mode
(peripheral mode or host mode).
Some of the bits in this register are valid only in host mode, while others are valid in
peripheral mode only. This register also indicates the current mode. To clear the interrupt
status bits of the rc_w1 type, the application must write 1 into the bit.
The FIFO status interrupts are read-only; once software reads from or writes to the FIFO
while servicing these interrupts, FIFO interrupt conditions are cleared automatically.
The application must clear the OTG_HS_GINTSTS register at initialization before
unmasking the interrupt bit to avoid any interrupts generated prior to initialization.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rc_w1 r r
Bit 31 WKUPINT: Resume/remote wakeup detected interrupt
Note: Accessible in both peripheral and host modes.
Bit 30 SRQINT: Session request/new session detected interrupt
Bit 29 DISCINT: Disconnect detected interrupt
Note: Only accessible in host mode.
Bit 28 CIDSCHG: Connector ID status change
Note: Accessible in both peripheral and host modes.
Bit 27 Reserved, must be kept at reset value.
Bit 26 PTXFE: Periodic TxFIFO empty
Note: Only accessible in host mode.
1404/1731
r rc_w1 r
In peripheral mode, this interrupt is asserted when a resume is detected on the USB. In host
mode, this interrupt is asserted when a remote wakeup is detected on the USB.
In host mode, this interrupt is asserted when a session request is detected from the device.
In peripheral mode, this interrupt is asserted when V
device. Accessible in both peripheral and host modes.
Asserted when a device disconnect is detected.
The core sets this bit when there is a change in connector ID status.
Asserted when the periodic transmit FIFO is either half or completely empty and there is
space for at least one entry to be written in the periodic request queue. The half or
completely empty status is determined by the periodic TxFIFO empty level bit in the Core
AHB configuration register (PTXFELVL bit in OTG_HS_GAHBCFG).
DocID018909 Rev 11
r rc_w1
9 8 7 6 5 4
r r r r
is in the valid range for a B-device
BUS
RM0090
3 2 1 0
r r