STMicroelectronics STM32F405 Reference Manual page 909

RM0090
28.5 SPI and I
Refer to Section: List of abbreviations for registers.
The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).
28.5.1 SPI control register 1 (SPI_CR1) (not used in I
Address offset: 0x00
Reset value: 0x0000
15 14 13
BIDI BIDI CRC CRC
MODE OE EN NEXT
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Bit 15 BIDIMODE: Bidirectional data mode enable
Note: This bit is not used in I
Bit 14 BIDIOE: Output enable in bidirectional mode
Note: This bit is not used in I
Bit 13 CRCEN: Hardware CRC calculation enable
Note: This bit should be written only when SPI is disabled (SPE = '0') for correct operation.
Bit 12 CRCNEXT: CRC transfer next
Note: When the SPI is configured in full duplex or transmitter only modes, CRCNEXT must be
Bit 11 DFF: Data frame format
Note: This bit should be written only when SPI is disabled (SPE = '0') for correct operation.
2
S registers
12 11 10 9
RX
DFF SSM
ONLY
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0: 2-line unidirectional data mode selected
1: 1-line bidirectional data mode selected
This bit combined with the BIDImode bit selects the direction of transfer in bidirectional mode
0: Output disabled (receive-only mode)
1: Output enabled (transmit-only mode)
In master mode, the MOSI pin is used while the MISO pin is used in slave mode.
0: CRC calculation disabled
1: CRC calculation enabled
2
It is not used in I S mode.
0: Data phase (no CRC phase)
1: Next transfer is CRC (CRC phase)
written as soon as the last data is written to the SPI_DR register.
When the SPI is configured in receiver only mode, CRCNEXT must be set after the
second last data reception.
This bit should be kept cleared when the transfers are managed by DMA.
2
It is not used in I S mode.
0: 8-bit data frame format is selected for transmission/reception
1: 16-bit data frame format is selected for transmission/reception
2
It is not used in I S mode.
DocID018909 Rev 11
8 7 6
LSB
SSI SPE
FIRST
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2
S mode
2
S mode.
Serial peripheral interface (SPI)
2
S mode)
5 4 3 2
BR [2:0] MSTR
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1 0
CPOL CPHA
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