STMicroelectronics STM32F405 Reference Manual page 1432

USB on-the-go high-speed (OTG_HS)
OTG_HS device control register (OTG_HS_DCTL)
Address offset: 0x804
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:12 Reserved, must be kept at reset value.
Bit 11 POPRGDNE: Power-on programming done
Bit 10 CGONAK: Clear global OUT NAK
Bit 9 SGONAK: Set global OUT NAK
Bit 8 CGINAK: Clear global IN NAK
Bit 7 SGINAK: Set global IN NAK
Bits 6:4 TCTL: Test control
Bit 3 GONSTS: Global OUT NAK status
1432/1731
Reserved
The application uses this bit to indicate that register programming is completed after a
wakeup from power down mode.
A write to this field clears the Global OUT NAK.
A write to this field sets the Global OUT NAK.
The application uses this bit to send a NAK handshake on all OUT endpoints.
The application must set the this bit only after making sure that the Global OUT NAK
effective bit in the Core interrupt register (GONAKEFF bit in OTG_HS_GINTSTS) is
cleared.
A write to this field clears the Global IN NAK.
A write to this field sets the Global nonperiodic IN NAK.The application uses this bit to send
a NAK handshake on all nonperiodic IN endpoints.
The application must set this bit only after making sure that the Global IN NAK effective bit
in the Core interrupt register (GINAKEFF bit in OTG_HS_GINTSTS) is cleared.
000: Test mode disabled
001: Test_J mode
010: Test_K mode
011: Test_SE0_NAK mode
100: Test_Packet mode
101: Test_Force_Enable
Others: Reserved
0: A handshake is sent based on the FIFO Status and the NAK and STALL bit settings.
1: No data is written to the RxFIFO, irrespective of space availability. Sends a NAK
handshake on all packets, except on SETUP transactions. All isochronous OUT packets are
dropped.
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