STMicroelectronics STM32F405 Reference Manual page 1443

RM0090
Bit 9 BIM: BNA interrupt mask
Bit 8 OPEM: OUT packet error mask
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 AHBERRM: AHB error mask
Bit 1 EPDM: Endpoint disabled interrupt mask
Bit 0 XFRCM: Transfer completed interrupt mask
OTG device endpoint-x control register (OTG_HS_DIEPCTLx) (x = 0..7, where
x = Endpoint_number)
Address offset: 0x900 + (Endpoint_number × 0x20)
Reset value: 0x0000 0000
The application uses this register to control the behavior of each logical endpoint other than
endpoint 0.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rs rs w w w w rw rw rw rw
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
TXFNUM
rw/
rw rw
rs
DocID018909 Rev 11
USB on-the-go high-speed (OTG_HS)
Reserved
r r rw
9 8 7 6 5 4
MPSIZ
rw rw rw rw rw rw rw rw rw rw rw
3 2 1 0
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