STMicroelectronics STM32F405 Reference Manual page 1413

Advanced arm-based 32-bit mcus
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RM0090
OTG_HS nonperiodic transmit FIFO size/Endpoint 0 transmit FIFO size
register (OTG_HS_GNPTXFSIZ/OTG_HS_TX0FSIZ)
Address offset: 0x028
Reset value: 0x0000 0200
Host mode:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:16 NPTXFD: Nonperiodic TxFIFO depth
This value is in terms of 32-bit words.
Minimum value is 16
Maximum value is 1024
Bits 15:0 NPTXFSA: Nonperiodic transmit RAM start address
This field contains the memory start address for nonperiodic transmit FIFO RAM.
Peripheral mode:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:16 T0XFD: Endpoint 0 TxFIFO depth
This value is in terms of 32-bit words.
Minimum value is 16
Maximum value is 256
Bits 15:0 TX0FSA: Endpoint 0 transmit RAM start address
This field contains the memory start address for Endpoint 0 transmit FIFO RAM.
OTG_HS nonperiodic transmit FIFO/queue status register
(OTG_HS_GNPTXSTS)
Address offset: 0x02C
Reset value: 0x0008 0200
Note:
In peripheral mode, this register is not valid.
This read-only register contains the free space information for the nonperiodic TxFIFO and
the nonperiodic transmit request queue.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
NPTXQTOP
r
NPTXFD
r/rw
TX0FD
r/rw
NPTQXSAV
r
DocID018909 Rev 11
USB on-the-go high-speed (OTG_HS)
9
8
7
6
NPTXFSA
r/rw
9
8
7
6
TX0FSA
r/rw
9
8
7
6
NPTXFSAV
r
5
4
3
2
1
0
5
4
3
2
1
0
5
4
3
2
1
0
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