STMicroelectronics STM32F405 Reference Manual page 1724

Revision history
Date
28-Jul-2015
1724/1731
Table 310. Document revision history (continued)
Version
General-purpose timers (TIM9 to TIM14)
– Added the note in
(TIM9/12),
– Added the note to MMS2 bit description,
– Added the note to SMS[2:0] bit description in
TIM9/12 slave mode control register
Window watchdog (WWDG)
– Updated.Figure 214: Watchdog block diagram
Controller area network (bxCAN)
– Replaced tCAN with tq,
Flexible static memory controller (FSMC)
– Added the paragraph about Cross boundary page for Cellular RAM
1.5 in Section 36.5.5: Synchronous
10
– Updated MEMHIZx, MEMHOLDx, MEMSETx bit field descriptions
(Continued)
for FSMC_PME2..4 register in
transactions,
– Updated ATTSET, ATTHOLD, ATTHIZ bit field descriptions for
FSMC_PATT2..4 register in
transactions,
– Updated IRS and IFS bit descriptions for FMC_SR2..4 in
Section 36.5.5: Synchronous
– Renamed ADDSET as ADDSET[3:0] and MTYP as MTYP[1:0],
– Addition of CPSIZE in FSMC_BCRx bit fields in
FSMC_BCRx bit
Table 226: FSMC_BCRx bit
fields, Table 232: FSMC_BCRx bit
bit fields,
– Added CPIZE[2:0] in FMC_BCR1...4 registers in
NOR/PSRAM control registers
– Added CPSIZE[2:0] for FMC_BCRx registers in
FSMC register
DocID018909 Rev 11
Changes
Section 19.3.12: Timer synchronization
Section 36.5.5: Synchronous
Section 36.5.5: Synchronous
transactions,
fields, Table 223: FSMC_BCRx bit
fields,
Table 237: FSMC_BCRx bit
Section NOR/PSRAM control re
map.
RM0090
Section 19.4.2:
(TIMx_SMCR).
transactions,
Table 221:
fields,
Table 229: FSMC_BCRx bit
fields, Table 235: FSMC_BCRx
fields,
,Section 36.5.6:
Section 36.6.9: