STMicroelectronics STM32F405 Reference Manual page 1406

USB on-the-go high-speed (OTG_HS)
Bit 19 OEPINT: OUT endpoint interrupt
Note: Only accessible in peripheral mode.
Bit 18 IEPINT: IN endpoint interrupt
Note: Only accessible in peripheral mode.
Bits 17:16 Reserved, must be kept at reset value.
Bit 15 EOPF: End of periodic frame interrupt
Note: Only accessible in peripheral mode.
Bit 14 ISOODRP: Isochronous OUT packet dropped interrupt
Note: Only accessible in peripheral mode.
Bit 13 ENUMDNE: Enumeration done
Note: Only accessible in peripheral mode.
Bit 12 USBRST: USB reset
Note: Only accessible in peripheral mode.
Bit 11 USBSUSP: USB suspend
Note: Only accessible in peripheral mode.
Bit 10 ESUSP: Early suspend
Note: Only accessible in peripheral mode.
Bits 9:8
1406/1731
The core sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of
the core (in peripheral mode). The application must read the device all endpoints interrupt
(OTG_HS_DAINT) register to determine the exact number of the OUT endpoint on which
the interrupt occurred, and then read the corresponding device OUT Endpoint-x Interrupt
(OTG_HS_DOEPINTx) register to determine the exact cause of the interrupt. The
application must clear the appropriate status bit in the corresponding OTG_HS_DOEPINTx
register to clear this bit.
The core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the
core (in peripheral mode). The application must read the device All Endpoints Interrupt
(OTG_HS_DAINT) register to determine the exact number of the IN endpoint on which the
interrupt occurred, and then read the corresponding device IN Endpoint-x interrupt
(OTG_HS_DIEPINTx) register to determine the exact cause of the interrupt. The application
must clear the appropriate status bit in the corresponding OTG_HS_DIEPINTx register to
clear this bit.
Indicates that the period specified in the periodic frame interval field of the device
configuration register (PFIVL bit in OTG_HS_DCFG) has been reached in the current frame.
The core sets this bit when it fails to write an isochronous OUT packet into the RxFIFO
because the RxFIFO does not have enough space to accommodate a maximum size packet
for the isochronous OUT endpoint.
The core sets this bit to indicate that speed enumeration is complete. The application must
read the device Status (OTG_HS_DSTS) register to obtain the enumerated speed.
The core sets this bit to indicate that a reset is detected on the USB.
The core sets this bit to indicate that a suspend was detected on the USB. The core enters
the Suspended state when there is no activity on the data lines for a period of 3 ms.
The core sets this bit to indicate that an Idle state has been detected on the USB for 3 ms.
Reserved, must be kept at reset value.
DocID018909 Rev 11
RM0090