STMicroelectronics STM32F405 Reference Manual page 1722

Revision history
Date
16-Mar-2015
1722/1731
Table 310. Document revision history (continued)
Version
I2C2:
Updated FREQ[5:0] description in
register 2 (I2C_CR2).
USART:
Removed note related to RXNEIE in
FSMC:
Updated Figure 472: Synchronous multiplexed read mode
waveforms - NOR, PSRAM
USB OTG FS
Updated Table 200: TRDT values
9
(continued)
FMC
Updated FMC_NL in
Updated 'Memory wait' and 'Memory data bus high-z' parameters in
Table 284: Programmable NAND Flash/PC Card access
parameters.
Updated Section : Common memory space timing register 2..4
(FMC_PMEM2..4).
Updated Figure 474: NAND Flash/PC Card controller waveforms for
common memory
DEBUG:
Updated REV_ID[15:0) and JTAG ID code in
device ID code
DocID018909 Rev 11
Changes
Section 27.6.2: I2C Control
Section : Reception using DMA
(CRAM).
Figure 454: FMC block
access.
and Section 38.6.2: Boundary scan
RM0090
diagram.
Section 38.6.1: MCU
TAP, respectively