STMicroelectronics STM32F405 Reference Manual page 1457

RM0090
Bit 31 Reserved, must be kept at reset value.
Bits 30:29 RXDPID: Received data PID
STUPCNT: SETUP packet count
Bit 28:19 PKTCNT: Packet count
Bits 18:0 XFRSIZ: Transfer size
OTG_HS device endpoint-x DMA address register (OTG_HS_DIEPDMAx /
OTG_HS_DOEPDMAx) (x = 1..5, where x = Endpoint_number)
Address offset for IN endpoints: 0x914 + (Endpoint_number × 0x20)
Reset value: 0xXXXX XXXX
Address offset for OUT endpoints: 0xB14 + (Endpoint_number × 0x20)
Reset value: 0xXXXX XXXX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:0 DMAADDR: DMA address
Note: For control endpoints, this field stores control OUT data packets as well as SETUP
Applies to isochronous OUT endpoints only.
This is the data PID received in the last packet for this endpoint.
00: DATA0
01: DATA2
10: DATA1
11: MDATA
Applies to control OUT Endpoints only.
This field specifies the number of back-to-back SETUP data packets the endpoint can
receive.
01: 1 packet
10: 2 packets
11: 3 packets
Indicates the total number of USB packets that constitute the Transfer Size amount of data
for this endpoint.
This field is decremented every time a packet (maximum size or short packet) is written to
the RxFIFO.
This field contains the transfer size in bytes for the current endpoint. The core only interrupts
the application after it has exhausted the transfer size amount of data. The transfer size can
be set to the maximum packet size of the endpoint, to be interrupted at the end of each
packet.
The core decrements this field every time a packet is read from the RxFIFO and written to
the external memory.
This bit holds the start address of the external memory for storing or fetching endpoint data.
transaction data packets. When more than three SETUP packets are received back-to-
back, the SETUP data packet in the memory is overwritten. This register is incremented
on every AHB transaction. The application can give only a DWORD-aligned address.
DocID018909 Rev 11
USB on-the-go high-speed (OTG_HS)
DMAADDR
9 8 7 6 5 4 3
1457/1731
2 1 0
1529