STMicroelectronics STM32F405 Reference Manual page 1003

RM0090
Bits 31:16 Reserved, must be kept at reset value
Bit 15 OVER8: Oversampling mode
Note: Oversampling by 8 is not available in the Smartcard, IrDA and LIN modes: when
Bit 14 Reserved, must be kept at reset value
Bit 13 UE: USART enable
Bit 12 M: Word length
Note: The M bit must not be modified during a data transfer (both transmission and reception)
Bit 11 WAKE: Wakeup method
Bit 10 PCE: Parity control enable
Bit 9 PS: Parity selection
Bit 8 PEIE: PE interrupt enable
Bit 7 TXEIE: TXE interrupt enable
Bit 6 TCIE: Transmission complete interrupt enable
Universal synchronous asynchronous receiver transmitter (USART)
0: oversampling by 16
1: oversampling by 8
SCEN=1,IREN=1 or LINEN=1 then OVER8 is forced to '0 by hardware.
When this bit is cleared, the USART prescalers and outputs are stopped and the end of the
current byte transfer in order to reduce power consumption. This bit is set and cleared by
software.
0: USART prescaler and outputs disabled
1: USART enabled
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 Data bits, n Stop bit
1: 1 Start bit, 9 Data bits, n Stop bit
This bit determines the USART wakeup method, it is set or cleared by software.
0: Idle Line
1: Address Mark
This bit selects the hardware parity control (generation and detection). When the parity
control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit
if M=0) and parity is checked on the received data. This bit is set and cleared by software.
Once it is set, PCE is active after the current byte (in reception and in transmission).
0: Parity control disabled
1: Parity control enabled
This bit selects the odd or even parity when the parity generation/detection is enabled (PCE
bit set). It is set and cleared by software. The parity will be selected after the current byte.
0: Even parity
1: Odd parity
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated whenever PE=1 in the USART_SR register
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated whenever TXE=1 in the USART_SR register
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated whenever TC=1 in the USART_SR register
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