STMicroelectronics STM32F405 Reference Manual page 1292

Advanced arm-based 32-bit mcus
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USB on-the-go full-speed (OTG_FS)
Bit 2 Reserved, must be kept at reset value.
Bit 1 CHHM: Channel halted mask
Bit 0 XFRCM: Transfer completed mask
OTG_FS Host channel-x transfer size register (OTG_FS_HCTSIZx) (x = 0..7,
where x = Channel_number)
Address offset: 0x510 + (Channel_number × 0x20)
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DPID
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:29 DPID: Data PID
Bits 28:19 PKTCNT: Packet count
Bits 18:0 XFRSIZ: Transfer size
1292/1731
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
PKTCNT
The application programs this field with the type of PID to use for the initial transaction. The
host maintains this field for the rest of the transfer.
00: DATA0
01: DATA2
10: DATA1
11: MDATA (non-control)/SETUP (control)
This field is programmed by the application with the expected number of packets to be
transmitted (OUT) or received (IN).
The host decrements this count on every successful transmission or reception of an OUT/IN
packet. Once this count reaches zero, the application is interrupted to indicate normal
completion.
For an OUT, this field is the number of data bytes the host sends during the transfer.
For an IN, this field is the buffer size that the application has reserved for the transfer. The
application is expected to program this field as an integer multiple of the maximum packet
size for IN transactions (periodic and non-periodic).
DocID018909 Rev 11
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XFRSIZ
RM0090
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2
1
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