STMicroelectronics STM32F405 Reference Manual page 1201

RM0090
Ethernet MAC address 3 high register (ETH_MACA3HR)
Address offset: 0x0058
Reset value: 0x0000 FFFF
The MAC address 3 high register holds the upper 16 bits of the 6-byte second MAC address
of the station.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
AE SA MBC
rw rw rw rw rw rw rw rw
Bit 31 AE: Address enable
When this bit is set, the address filters use the MAC address3 for perfect filtering. When this
bit is cleared, the address filters ignore the address for filtering.
Bit 30 SA: Source address
When this bit is set, the MAC address 3 [47:0] is used for comparison with the SA fields of the
received frame.
When this bit is cleared, the MAC address 3[47:0] is used for comparison with the DA fields
of the received frame.
Bits 29:24 MBC: Mask byte control
These bits are mask control bits for comparison of each of the MAC address3 bytes. When
these bits are set high, the MAC core does not compare the corresponding byte of received
DA/SA with the contents of the MAC address 3 registers. Each bit controls the masking of the
bytes as follows:
– Bit 29: ETH_MACA3HR [15:8]
– Bit 28: ETH_MACA3HR [7:0]
– Bit 27: ETH_MACA3LR [31:24]
...
– Bit 24: ETH_MACA3LR [7:0]
Bits 23:16 Reserved, must be kept at reset value.
Bits 15:0 MACA3H: MAC address3 high [47:32]
This field contains the upper 16 bits (47:32) of the 6-byte MAC address3.
Ethernet MAC address 3 low register (ETH_MACA3LR)
Address offset: 0x005C
Reset value: 0xFFFF FFFF
The MAC address 3 low register holds the lower 32 bits of the 6-byte second MAC address
of the station.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 MACA3L: MAC address3 low [31:0]
Ethernet (ETH): media access control (MAC) with DMA controller
Reserved
This field contains the lower 32 bits of the 6-byte second MAC address3. The content of this
field is undefined until loaded by the application after the initialization process.
DocID018909 Rev 11
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
MACA3L
9 8 7 6 5 4 3
MACA3H
9 8 7 6 5 4 3
2 1 0
2 1 0
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