STMicroelectronics STM32F405 Reference Manual page 1718

Revision history
Date
15-May-2014
1718/1731
Table 310. Document revision history (continued)
Version
FMC
Updated Figure 472: Synchronous multiplexed read mode
waveforms - NOR, PSRAM
in Section : SRAM/NOR-Flash chip-select timing registers 1..4
(FMC_BTR1..4).
7
Updated FMC_BWTRx register address offsets in
(continued)
register map.
DEBUG
Added revision code '3' in
DocID018909 Rev 11
Changes
(CRAM). Updated DATLAT bits definition
Section : DBGMCU_IDCODE.
RM0090
Table 292: FMC