STMicroelectronics STM32F405 Reference Manual page 1405

RM0090
Bit 25 HCINT: Host channels interrupt
Note: Only accessible in host mode.
Bit 24 HPRTINT: Host port interrupt
Note: Only accessible in host mode.
Bits 23 Reserved, must be kept at reset value.
Bit 22 DATAFSUSP: Data fetch suspended
Bit 21 IPXFR: Incomplete periodic transfer
Note: Only accessible in host mode.
INCOMPISOOUT: Incomplete isochronous OUT transfer
Note: Only accessible in peripheral mode.
Bit 20 IISOIXFR: Incomplete isochronous IN transfer
Note: Only accessible in peripheral mode.
The core sets this bit to indicate that an interrupt is pending on one of the channels of the
core (in host mode). The application must read the host all channels interrupt
(OTG_HS_HAINT) register to determine the exact number of the channel on which the
interrupt occurred, and then read the corresponding host channel-x interrupt
(OTG_HS_HCINTx) register to determine the exact cause of the interrupt. The application
must clear the appropriate status bit in the OTG_HS_HCINTx register to clear this bit.
The core sets this bit to indicate a change in port status of one of the OTG_HS controller
ports in host mode. The application must read the host port control and status
(OTG_HS_HPRT) register to determine the exact event that caused this interrupt. The
application must clear the appropriate status bit in the host port control and status register to
clear this bit.
This interrupt is valid only in DMA mode. This interrupt indicates that the core has stopped
fetching data for IN endpoints due to the unavailability of TxFIFO space or request queue
space. This interrupt is used by the application for an endpoint mismatch algorithm. For
example, after detecting an endpoint mismatch, the application:
– Sets a global nonperiodic IN NAK handshake
– Disables IN endpoints
– Flushes the FIFO
– Determines the token sequence from the IN token sequence learning queue
– Re-enables the endpoints
– Clears the global nonperiodic IN NAK handshake If the global nonperiodic IN NAK
is cleared, the core has not yet fetched data for the IN endpoint, and the IN token is
received: the core generates an "IN token received when FIFO empty" interrupt.
The OTG then sends a NAK response to the host. To avoid this scenario, the
application can check the FetSusp interrupt in OTG_FS_GINTSTS, which ensures
that the FIFO is full before clearing a global NAK handshake. Alternatively, the
application can mask the "IN token received when FIFO empty" interrupt when
clearing a global IN NAK handshake.
In host mode, the core sets this interrupt bit when there are incomplete periodic transactions
still pending, which are scheduled for the current frame.
In peripheral mode, the core sets this interrupt to indicate that there is at least one
isochronous OUT endpoint on which the transfer is not completed in the current frame. This
interrupt is asserted along with the End of periodic frame interrupt (EOPF) bit in this register.
The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on
which the transfer is not completed in the current frame. This interrupt is asserted along with
the End of periodic frame interrupt (EOPF) bit in this register.
DocID018909 Rev 11
USB on-the-go high-speed (OTG_HS)
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