STMicroelectronics STM32F405 Reference Manual page 1093

RM0090
Bit 7 ABRQ0
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 TERR0
Bit 2 ALST0
Bit 1 TXOK0
Bit 0 RQCP0
CAN receive FIFO 0 register (CAN_RF0R)
Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29
15 14 13
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 RFOM0
Bit 4 FOVR0
Bit 3 FULL0
Bit 2 Reserved, must be kept at reset value.
:
Abort request for mailbox0
Set by software to abort the transmission request for the corresponding mailbox.
Cleared by hardware when the mailbox becomes empty.
Setting this bit has no effect when the mailbox is not pending for transmission.
:
Transmission error of mailbox0
This bit is set when the previous TX failed due to an error.
:
Arbitration lost for mailbox0
This bit is set when the previous TX failed due to an arbitration lost.
:
Transmission OK of mailbox0
The hardware updates this bit after each transmission attempt.
0: The previous transmission failed
1: The previous transmission was successful
This bit is set by hardware when the transmission request on mailbox 1 has been completed
successfully. Please refer to
:
Request completed mailbox0
Set by hardware when the last request (transmit or abort) has been performed.
Cleared by software writing a "1" or by hardware on transmission request (TXRQ0 set in
CAN_TI0R register).
Clearing this bit clears all the status bits (TXOK0, ALST0 and TERR0) for Mailbox 0.
28 27 26 25
12 11 10 9
Reserved
:
Release FIFO 0 output mailbox
Set by software to release the output mailbox of the FIFO. The output mailbox can only be
released when at least one message is pending in the FIFO. Setting this bit when the FIFO
is empty has no effect. If at least two messages are pending in the FIFO, the software has to
release the output mailbox to access the next message.
Cleared by hardware when the output mailbox has been released.
:
FIFO 0 overrun
This bit is set by hardware when a new message has been received and passed the filter
while the FIFO was full.
This bit is cleared by software.
:
FIFO 0 full
Set by hardware when three messages are stored in the FIFO.
This bit is cleared by software.
DocID018909 Rev 11
Figure 340
24 23 22 21
Reserved
8 7 6 5
RFOM0 FOVR0 FULL0
rs
Controller area network (bxCAN)
20 19 18
4 3 2
Res.
rc_w1 rc_w1
17 16
1 0
FMP0[1:0]
r r
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