STMicroelectronics STM32F405 Reference Manual page 752

Cryptographic processor (CRYP)
CRYP_IV1LR (address offset: 0x48)
31 30 29
IV64 IV65 IV66 IV67
rw rw rw
15 14 13
IV80 IV81 IV82 IV83
rw rw rw
CRYP_IV1RR (address offset: 0x4C)
31 30 29
IV96 IV97 IV98 IV99
rw rw rw
15 14 13
IV112 IV113 IV114 IV115
rw rw rw
Note: In DES/3DES modes, only CRYP_IV0(L/R) is used.
Write access to these registers are disregarded when the cryptographic processor is busy
(bit BUSY = 1 in the CRYP_SR register).
752/1731
28 27 26 25
IV68 IV69 IV70
rw rw rw rw
12 11 10 9
IV84 IV85 IV86
rw rw rw rw
28 27 26 25
IV100 IV101 IV102
rw rw rw rw
12 11 10 9
IV116 IV117 IV118
rw rw rw rw
DocID018909 Rev 11
24 23 22 21
IV71 IV72 IV73 IV74
rw rw rw rw
8 7 6 5
IV87 IV88 IV89 IV90
rw rw rw rw
24 23 22 21
IV103 IV104 IV105 IV106
rw rw rw rw
8 7 6 5
IV119 IV120 IV121 IV122
rw rw rw rw
20 19 18 17
IV75 IV76 IV77 IV78
rw rw rw rw
4 3 2 1
IV91 IV92 IV93 IV94
rw rw rw rw
20 19 18 17
IV107 IV108 IV109 IV110
rw rw rw rw
4 3 2 1
IV123 IV124 IV125 IV126
rw rw rw rw
RM0090
16
IV79
rw
0
IV95
rw
16
IV111
rw
0
IV127
rw