STMicroelectronics STM32F405 Reference Manual page 1228

Ethernet (ETH): media access control (MAC) with DMA controller
Ethernet DMA current host transmit descriptor register (ETH_DMACHTDR)
Address offset: 0x1048
Reset value: 0x0000 0000
The Current host transmit descriptor register points to the start address of the current
transmit descriptor read by the DMA.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r r r r r r r
Bits 31:0 HTDAP: Host transmit descriptor address pointer
Ethernet DMA current host receive descriptor register (ETH_DMACHRDR)
Address offset: 0x104C
Reset value: 0x0000 0000
The Current host receive descriptor register points to the start address of the current receive
descriptor read by the DMA.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r r r r r r r
Bits 31:0 HRDAP: Host receive descriptor address pointer
Ethernet DMA current host transmit buffer address register
Address offset: 0x1050
Reset value: 0x0000 0000
The Current host transmit buffer address register points to the current transmit buffer
address being read by the DMA.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r r r r r r r
Bits 31:0 HTBAP: Host transmit buffer address pointer
1228/1731
r r r r r r
Cleared . Pointer updated by DMA during operation.
r r r r r r
Cleared On Reset. Pointer updated by DMA during operation.
(ETH_DMACHTBAR)
r r r r r r
Cleared On Reset. Pointer updated by DMA during operation.
DocID018909 Rev 11
HTDAP
r r r r r r r
HRDAP
r r r r r r r
HTBAP
r r r r r r r
9 8 7 6 5
r r r r r r r
9 8 7 6 5
r r r r r r r
9 8 7 6 5
r r r r r r r
RM0090
4 3 2 1 0
r r r r r
4 3 2 1 0
r r r r r
4 3 2 1 0
r r r r r