STMicroelectronics STM32F405 Reference Manual page 1424

USB on-the-go high-speed (OTG_HS)
Bit 2 PENA: Port enable
Bit 1 PCDET: Port connect detected
Bit 0 PCSTS: Port connect status
OTG_HS host channel-x characteristics register (OTG_HS_HCCHARx)
(x = 0..11, where x = Channel_number)
Address offset: 0x500 + (Channel_number × 0x20)
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DAD
rs rs rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 31 CHENA: Channel enable
Bit 30 CHDIS: Channel disable
Bit 29 ODDFRM: Odd frame
Bits 28:22 DAD: Device address
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A port is enabled only by the core after a reset sequence, and is disabled by an overcurrent
condition, a disconnect condition, or by the application clearing this bit. The application
cannot set this bit by a register write. It can only clear it to disable the port. This bit does not
trigger any interrupt to the application.
0: Port disabled
1: Port enabled
The core sets this bit when a device connection is detected to trigger an interrupt to the
application using the host port interrupt bit in the Core interrupt register (HPRTINT bit in
OTG_HS_GINTSTS). The application must write a 1 to this bit to clear the interrupt.
0: No device is attached to the port
1: A device is attached to the port
MC
This field is set by the application and cleared by the OTG host.
0: Channel disabled
1: Channel enabled
The application sets this bit to stop transmitting/receiving data on a channel, even before
the transfer for that channel is complete. The application must wait for the Channel disabled
interrupt before treating the channel as disabled.
This field is set (reset) by the application to indicate that the OTG host must perform a
transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt)
transactions.
0: Even (micro) frame
1: Odd (micro) frame
This field selects the specific device serving as the data source or sink.
DocID018909 Rev 11
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EPNUM
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RM0090
8 7 6 5 4 3 2
MPSIZ
1 0