STMicroelectronics STM32F405 Reference Manual page 1717

RM0090
Date
15-May-2014
Table 310. Document revision history (continued)
Version
Embedded Flash memory interface:
Updated Section : Physical remap in STM32F42xxx and
STM32F43xxx. Updated bank 2 selection in
configuration. Updated notes related to MERx and SER bits in
Section : Mass
readout protection
reset value for STM32F42/43xx in
control register (FLASH_OPTCR) for STM32F42xxx and
STM32F43xxx
(FLASH_OPTCR1) for STM32F42xxx and
RCC (STM32F42/43xx):
Updated PPLN caution note in
register (RCC_PLLCFGR)
SYSCFG
Updated MEM_MODE in
register (SYSCFG_MEMRMP)
LTDC:
Changed resolution do XGA (1024x768) in
features, Section 16.4.1: LTDC Global configuration
updated Section 16.7.3: LTDC Active Width Configuration Register
(LTDC_AWCR).
7
RTC
Added note in
TIMER 1/8:
Removed note related to IC1F bits in
capture/compare mode register 1
TIM2 to 5:
Replaced IC2S by CC2S.
Updated Figure 161: Output stage of capture/compare channel
(channel 1). Removed note related to IC1F bits in
TIMx capture/compare mode register 1
TIM9 to 14:
Removed note related to IC1F bits in
capture/compare mode register 1
USB OTG-HS:
Updated DSPD definition in
register (OTG_HS_DCFG).
FSMC
Updated DATLAT bits definition in
select timing registers 1..4
DocID018909 Rev 11
Changes
Erase. Updated Section 3.7.5: Proprietary code
(PCROP). Updated FLASH_OPTCR register
Section 3.9.10: Flash option
and Section 3.9.11: Flash option control register
Section 6.3.2: RCC PLL configuration
Section 9.3.1: SYSCFG memory remap
Section 26.3.14: Calibration clock
Section 17.4.7: TIM1&TIM8
(TIMx_CCMR1),
Section 19.5.5: TIM10/11/13/14
(TIMx_CCMR1).
Section : OTG_HS device configuration
Section : SRAM/NOR-Flash chip-
(FSMC_BTR1..4).
Revision history
Section 2.4: Boot
STM32F43xxx.
Section 16.2: LTDC main
parameters, and
output.
Section 18.4.7:
(TIMx_CCMR1).
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