STMicroelectronics STM32F405 Reference Manual page 1446

USB on-the-go high-speed (OTG_HS)
OTG_HS device control OUT endpoint 0 control register
(OTG_HS_DOEPCTL0)
Address offset: 0xB00
Reset value: 0x0000 8000
This section describes the device control OUT endpoint 0 control register. Nonzero control
endpoints use registers for endpoints 1–15.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
w r w w
Bit 31 EPENA: Endpoint enable
– SETUP phase done
– Endpoint disabled
– Transfer completed
Bit 30 EPDIS: Endpoint disable
Bits 29:28 Reserved, must be kept at reset value.
Bit 27 SNAK: Set NAK
Bit 26 CNAK: Clear NAK
Bits 25:22 Reserved, must be kept at reset value.
Bit 21 STALL: STALL handshake
Bit 20 SNPM: Snoop mode
Bits 19:18 EPTYP: Endpoint type
1446/1731
EPTYP
Reserved
rs rw r
The application sets this bit to start transmitting data on endpoint 0.
The core clears this bit before setting any of the following interrupts on this endpoint:
The application cannot disable control OUT endpoint 0.
A write to this bit sets the NAK bit for the endpoint.
Using this bit, the application can control the transmission of NAK handshakes on an
endpoint. The core can also set this bit on a Transfer completed interrupt, or after a SETUP
is received on the endpoint.
A write to this bit clears the NAK bit for the endpoint.
The application can only set this bit, and the core clears it, when a SETUP token is received
for this endpoint. If a NAK bit or Global OUT NAK is set along with this bit, the STALL bit
takes priority. Irrespective of this bit's setting, the core always responds to SETUP data
packets with an ACK handshake.
This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check
the correctness of OUT packets before transferring them to application memory.
Hardcoded to 2'b00 for control.
DocID018909 Rev 11
r r r
9 8 7 6 5 4 3
Reserved
RM0090
2 1 0
MPSIZ
r r