STMicroelectronics STM32F405 Reference Manual page 1714

Revision history
Date
15-Sep-2013
1714/1731
Table 310. Document revision history (continued)
Version
USB OTG-FS:
Removed note related to VDD range limitation below
OTG A-B device connection
connection.
FSMC:
Updated Table
Replaced all occurences of DATALAT by DATLAT and SRAM/CRAM
by SRAM/PSRAM in the whole section.
Updated Section 36.1: FSMC main
of FSMC_BWTR1..4 to reserved.
Updated Section 36.6.7: PC Card/CompactFlash
Updated WREN bit in
5 Table 234,
(continued)
Updated Section 36.5.4: NOR Flash/PSRAM controller
asynchronous
control registers 1..4
chip-select timing registers 1..4 (FSMC_BTR1..4)
SRAM/NOR-Flash write timing registers 1..4
Updated definition of PWID in
registers 2..4
FMC:
Updated TRDC definition in
(FMC_SDTR1,2).
DEBUG: updated
DocID018909 Rev 11
Changes
and Figure 388: USB peripheral-only
224, Table 227, Table
Table 226, Table
Table 237, Table 240, and
transactions, Section : SRAM/NOR-Flash chip-select
(FSMC_BCR1..4),
Section : PC Card/NAND Flash control
(FSMC_PCR2..4).
Section : SDRAM Timing registers 1,2
Figure 485: JTAG TAP
Figure 387:
230, Table 234.
features. Changed bits 27 to 20
operations.
227, Table 228, Table
Table 244.
Section : SRAM/NOR-Flash
and Section :
(FSMC_BWTR1..4).
connections.
RM0090
231,