STMicroelectronics STM32F405 Reference Manual page 1716

Revision history
Date
03-Feb-2014
1716/1731
Table 310. Document revision history (continued)
Version
TIM9 to 14:
Updated note related to IC1F in
capture/compare mode register 1
RTC:
Updated Section 26.3.11: RTC smooth digital
Changed ALRBIE to ALRBE (bit 9) in
register (RTC_CR).
I2C:
Introduced Sm (standard mode) and Fm (fast mode) acronyms.
FSMC:
Updated BUSTURN definition in
6
FMC:
(continued)
Added Mobile LPSDR SDRAM.
Updated Section : SDRAM initialization
controller read cycle
controller waveforms for common memory
Updated Section : SRAM/NOR-Flash chip-select control registers
1..4 (FMC_BCR1..4),
registers 1..4
timing registers 1..4
registers 1,2 (FMC_SDTR1,2)
register (FMC_SDRTR).
Removed mention "default valeur after reset" in
memory space timing register 2..4
Attribute memory space timing registers 2..4
Section : I/O space timing register 4
Updated BUSTURN definition in
Updated REV_ID bits in
DocID018909 Rev 11
Changes
Section 19.5.5: TIM10/11/13/14
(TIMx_CCMR1).
Table 240: FSMC_BTRx bit
and Figure 474: NAND Flash/PC Card
Section : SRAM/NOR-Flash chip-select timing
(FMC_BTR1..4), Section : SRAM/NOR-Flash write
(FMC_BWTR1..4),
and Section : SDRAM Refresh Timer
(FMC_PMEM2..4),
(FMC_PIO4).
Table 283: FMC_BTRx bit
Section 38.6.1: MCU device ID
RM0090
calibration.
Section 26.6.3: RTC control
fields.
and Section : SDRAM
access.
Section : SDRAM Timing
Section : Common
Section :
(FMC_PATT2..4), and
fields.
code..