STMicroelectronics STM32F405 Reference Manual page 1193

RM0090
Ethernet MAC PMT control and status register (ETH_MACPMTCSR)
Address offset: 0x002C
Reset value: 0x0000 0000
The ETH_MACPMTCSR programs the request wakeup events and monitors the wakeup
events.
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rs
Bit 31 WFFRPR: Wakeup frame filter register pointer reset
Bits 30:10 Reserved, must be kept at reset value.
Bit 9 GU: Global unicast
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 WFR: Wakeup frame received
Bit 5 MPR: Magic packet received
Bits 4:3 Reserved, must be kept at reset value.
Bit 2 WFE: Wakeup frame enable
Bit 1 MPE: Magic Packet enable
Bit 0 PD: Power down
Ethernet (ETH): media access control (MAC) with DMA controller
Reserved
Res.
When set, it resets the Remote wakeup frame filter register pointer to 0b000. It is
automatically cleared after 1 clock cycle.
When set, it enables any unicast packet filtered by the MAC (DAF) address recognition to be
a wakeup frame.
When set, this bit indicates the power management event was generated due to reception of
a wakeup frame. This bit is cleared by a read into this register.
When set, this bit indicates the power management event was generated by the reception of
a Magic Packet. This bit is cleared by a read into this register.
When set, this bit enables the generation of a power management event due to wakeup
frame reception.
When set, this bit enables the generation of a power management event due to Magic
Packet reception.
When this bit is set, all received frames will be dropped. This bit is cleared automatically
when a magic packet or wakeup frame is received, and Power-down mode is disabled.
Frames received after this bit is cleared are forwarded to the application. This bit must only
be set when either the Magic Packet Enable or Wakeup Frame Enable bit is set high.
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