STMicroelectronics STM32F405 Reference Manual page 1706

Revision history
Date
19-Oct-2012
1706/1731
Table 310. Document revision history (continued)
Version
General purpose timers (TIM2 to TIM5):
Removed all references to "repetition counter".
Added Figure 134: General-purpose timer block
Updated 16-bit prescaler range in
features.
External clock mode 2 ETR restricted to TIM2 to TIM4 in
Section 18.3.3: Clock selection
mode.
Updated Section 18.3.9: PWM mode
the OCxREF signal on an external
Updated Figure 174: Master/Slave timer example
ITR0.
Updated read and write access to registers in
TIM5 registerss.
Restored bits 15 to 8 of TIMx_SMCR as well as
internal trigger connection
Removed note 1 related to OC1M bits in
capture/compare register 1
Updated TIMx_CCER bit description for TIM2 to TIM5 in
Section 18.4.9: TIMx capture/compare enable register
2
(TIMx_CCER).
(continued)
General purpose timers (TIM9 to TIM14):
Updated 16-bit prescaler range in
features and
features.
Updated Figure 181: General-purpose timer block diagram
(TIM10/11/13/14))
Added register access in
and Section 19.5: TIM10/11/13/14
Basic timers (TIM6 and TIM7):
Removed all references to "repetition counter".
Updated 16-bit prescaler range in
features.
HASH:
Updated Section 25.3.1: Duration of the
RNG:
Updated Section 24.1: RNG
DocID018909 Rev 11
Changes
Section 18.2: TIM2 to TIM5 main
and Section 18.3.6: PWM input
event.
in Section
(TIMx_CCR1).
Section 19.2.1: TIM9/TIM12 main
Section 19.2.2: TIM10/TIM11 and TIM13/TIM14 main
to remove TRGO trigger controller output.
Section 19.4: TIM9 and TIM12 registers
registers.
Section 20.2: TIM6&TIM7 main
introduction.
RM0090
diagram.
and Section 18.3.11: Clearing
to change ITR1 to
Section 18.4: TIM2 to
Table 97: TIMx
14.4.3.
Section 18.4.13: TIMx
processing.