STMicroelectronics STM32F405 Reference Manual page 1726

Revision history
Date
20-Oct-2015
1726/1731
Table 310. Document revision history (continued)
Version
Reset and clock controller (RCC)
Updated STM32F405/407/415/417xx
Updated
General purpuse I/O (GPIOs)
Changed definition of OSPEEDR bits in
output speed register (GPIOx_OSPEEDR) (x =
LCD-TFT display controller (LTDC):
Changed LRDC_IER into LTDC_IER in
interrupts.
Updated AHBP[11:0], AAV[11:0 and TOTALW[11:0 in
register map and reset
Controller area network (bxCAN):
Updated Section 32.3.4: Acceptance filters
Identifier filtering.
Flexible static memory controller (FSMC)
Updated BUSTURN description in
11
timing registers 1..4 (FSMC_BWTR1..4)
Flash chip-select timing registers 1..4 (FSMC_BTR1..4)
Updated note related to IRS and IFS bits in
and interrupt register 2..4
Flexible memory controller (FMC)
Updated paragraph related to the cacheable read FIFO in
SDRAM controller read
Updated BUSTURN description in
timing registers 1..4 (FMC_BWTR1..4)
Flash chip-select timing registers 1..4
Updated note related to IRS and IFS bits in
and interrupt register 2..4
Real-time clock (RTC2)
Updated WUCKSEL prescaler input in
diagram.
Updated 3rd step in
Updated WUTWF bit definition in
and status register
DocID018909 Rev 11
Changes
Figure 21: Clock
Section 8.4.3: GPIO port
Section 16.5: LTDC
values.
Section : SRAM/NOR-Flash write
and
(FSMC_SR2..4).
cycle.
Section : SRAM/NOR-Flash write
and
(FMC_BTR1..4).
(FMC_SR2..4).
Figure 237: RTC block
Section : Programming the wakeup
Section 26.6.4: RTC initialization
(RTC_ISR).
RM0090
tree.
A..I/J/K).
Table 91: LTDC
and Section 32.7.4:
Section : SRAM/NOR-
Section : FIFO status
Section :
Section : SRAM/NOR-
Section : FIFO status
timer.