STMicroelectronics STM32F405 Reference Manual page 1715

RM0090
Date
03-Feb-2014
Table 310. Document revision history (continued)
Version
Added note related to
2.1 V V
DD ran
frequency and Flash memory read
Updated maximum CPU frequency in
real-time memory accelerator (ART
PWR:
Updated Run mode/ over-drive mode in
regulator for STM32F42xxx and
RCC for STM32F42/43xx:
Changed APB1/2 and AHB maximum frequencies.xw
GPIOs:
Updated Figure 27: Selecting an alternate function on STM32F42xxx
and STM32F43xxx.
DMA:
Updated Section 10.3.7: Pointer incrementation
Single and burst
6 INTERRUPTS AND EVENTS:
Updated Table 62: Vector table for STM32F42xxx and
STM32F43xxx.
ADC:
Updated Section 13.3.10: Discontinuous mode/Section : Regular
group.
DCMI:
Updated Section 15.5.2: DCMI physical
LTDC:
Updated resolution in note below
timings.
TIM1 and 8:
Added note related to IC1F in
capture/compare mode register 1
TIM2 to 5:
Updated note related to IC1F in
capture/compare mode register 1
DocID018909 Rev 11
Changes
over-drive mode unavailable in 1.8 to
ge in Section 3.5.1: Relation between CPU clock
STM32F43xxx.
transfers..
Figure 82: LCD-TFT Synchronous
Section 17.4.7: TIM1&TIM8
(TIMx_CCMR1).
Section 18.4.7: TIMx
(TIMx_CCMR1).
Revision history
time.
Section 3.5.2: Adaptive
Accelerator™).
Section 5.1.4: Voltage
and Section 10.3.11:
interface.
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