STMicroelectronics STM32F405 Reference Manual page 1581

RM0090
Bits 5:4 PWID[1:0]: Databus width.
Defines the external memory device width.
Bit 3 PTYP: Memory type.
Defines the type of device attached to the corresponding memory bank:
Bit 2 PBKEN: PC Card/NAND Flash memory bank enable bit.
Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB
bus
Bit 1 PWAITEN: Wait feature enable bit.
Enables the Wait feature for the PC Card/NAND Flash memory bank:
Note: For a PC Card, when the wait feature is enabled, the MEMWAITx/ATTWAITx/IOWAITx
Bit 0
FIFO status and interrupt register 2..4 (FSMC_SR2..4)
Address offset: 0xA000 0000 + 0x44 + 0x20 * (x-1), x = 2..4
Reset value: 0x0000 0040
This register contains information about FIFO status and interrupt. The FSMC has a FIFO
that is used when writing to memories to store up to16 words of data from the AHB.
This is used to quickly write to the AHB and free it for transactions to peripherals other than
the FSMC, while the FSMC is draining its FIFO into the memory. This register has one of its
bits that indicates the status of the FIFO, for ECC purposes.
The ECC is calculated while the data are written to the memory, so in order to read the
correct ECC the software must wait until the FIFO is empty.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
00: 8 bits
01: 16 bits (default after reset). This value is mandatory for PC Cards.
10: reserved, do not use
11: reserved, do not use
0: PC Card, CompactFlash, CF+ or PCMCIA
1: NAND Flash (default after reset)
0: Corresponding memory bank is disabled (default after reset)
1: Corresponding memory bank is enabled
0: disabled
1: enabled
bits must be programmed to a value as follows:
≥
xxWAITx 4 + max_wait_assertion_time/HCLK
Where max_wait_assertion_time is the maximum time taken by NWAIT to go low once
nOE/nWE or nIORD/nIOWR is low.
Reserved, must be kept at reset value.
DocID018909 Rev 11
Flexible static memory controller (FSMC)
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