STMicroelectronics STM32F405 Reference Manual page 1008

Universal synchronous asynchronous receiver transmitter (USART)
Bit 2 IRLP: IrDA low-power
Bit 1 IREN: IrDA mode enable
Bit 0 EIE: Error interrupt enable
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This bit is used for selecting between normal and low-power IrDA modes
0: Normal mode
1: Low-power mode
This bit is set and cleared by software.
0: IrDA disabled
1: IrDA enabled
Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing
error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USART_SR register) in
case of Multi Buffer Communication (DMAR=1 in the USART_CR3 register).
0: Interrupt is inhibited
1: An interrupt is generated whenever DMAR=1 in the USART_CR3 register and FE=1 or
ORE=1 or NF=1 in the USART_SR register.
DocID018909 Rev 11
RM0090