STMicroelectronics STM32F405 Reference Manual page 1644

Flexible memory controller (FMC)
Bit 2 PBKEN: PC Card/NAND Flash memory bank enable bit.
Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB
bus
Bit 1 PWAITEN: Wait feature enable bit.
Enables the Wait feature for the PC Card/NAND Flash memory bank:
Note: For a PC Card, when the wait feature is enabled, the MEMWAITx/ATTWAITx/IOWAITx
Bit 0 Reserved.
FIFO status and interrupt register 2..4 (FMC_SR2..4)
Address offset: 0x44 + 0x20 * (x-1), x = 2..4
Reset value: 0x0000 0040
This register contains information about the FIFO status and interrupt. The FMC features a
FIFO that is used when writing to memories to transfer up to 16 words of data from the AHB.
This is used to quickly write to the FIFO and free the AHB for transactions to peripherals
other than the FMC, while the FMC is draining its FIFO into the memory. One of these
register bits indicates the status of the FIFO, for ECC purposes.
The ECC is calculated while the data are written to the memory. To read the correct ECC,
the software must consequently wait until the FIFO is empty.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:7 Reserved, must be kept at reset value
Bit 6 FEMPT: FIFO empty.
Read-only bit that provides the status of the FIFO
Bit 5 IFEN: Interrupt falling edge detection enable bit
Bit 4 ILEN: Interrupt high-level detection enable bit
1644/1731
0: Corresponding memory bank is disabled (default after reset)
1: Corresponding memory bank is enabled
0: disabled
1: enabled
bits must be programmed to a value as follows:
≥
xxWAITx 4 + max_wait_assertion_time/HCLK
Where max_wait_assertion_time is the maximum time taken by NWAIT to go low once
nOE/nWE or nIORD/nIOWR is low.
Reserved
0: FIFO not empty
1: FIFO empty
0: Interrupt falling edge detection request disabled
1: Interrupt falling edge detection request enabled
0: Interrupt high-level detection request disabled
1: Interrupt high-level detection request enabled
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