STMicroelectronics STM32F405 Reference Manual page 1214

Ethernet (ETH): media access control (MAC) with DMA controller
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 TSTTR: Time stamp target time reached
Bit 0 TSSO: Time stamp second overflow
Ethernet PTP PPS control register (ETH_PTPPPSCR)
Address offset: 0x072C
Reset value: 0x0000 0000
This register controls the frequency of the PPS output.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 PPSFREQ: PPS frequency selection
Note: If digital rollover is used (TSSSR=1, bit 9 in ETH_PTPTSCR), it is recommended not to
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When set, this bit indicates that the value of the system time is greater than or equal to the
value specified in the Target time high and low registers. This bit is cleared when the
ETH_PTPTSSR register is read.
When set, this bit indicates that the second value of the time stamp has overflowed beyond
0xFFFF FFFF.
Reserved
The PPS output frequency is set to 2
0000: 1 Hz with a pulse width of 125 ms for binary rollover and, of 100 ms for digital rollover
0001: 2 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)
0010: 4 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)
0011: 8 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)
0100: 16 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)
...
1111: 32768 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)
use the PPS output with a frequency other than 1 Hz. Otherwise, with digital rollover,
the PPS output has irregular waveforms at higher frequencies (though its average
frequency will always be correct during any one-second window).
DocID018909 Rev 11
9 8
PPSFREQ
Hz.
RM0090
7 6 5 4 3 2 1
PPSFREQ
ro
0
ro