STMicroelectronics STM32F405 Reference Manual page 1643

RM0090
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
Bits 31:20 Reserved, must be kept at reset value
Bits 19:17 ECCPS[2:0]: ECC page size.
Defines the page size for the extended ECC:
Bits 16:13 TAR[3:0]: ALE to RE delay.
Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period
Note: SET is MEMSET or ATTSET according to the addressed space.
Bits 12:9 TCLR[3:0]: CLE to RE delay.
Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
Note: SET is MEMSET or ATTSET according to the addressed space.
Bits 8:7 Reserved, must be kept at reset value
Bit 6 ECCEN: ECC computation logic enable bit
Bits 5:4 PWID[1:0]: Data bus width.
Defines the external memory device width.
Bit 3 PTYP: Memory type.
Defines the type of device attached to the corresponding memory bank:
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000: 256 byte
001: 512 byte
010: 1024 byte
011: 2048 byte
100: 4096 byte
101: 8192 byte
0000: 1 HCLK cycle (default)
1111: 16 HCLK cycles
0000: 1 HCLK cycle (default)
1111: 16 HCLK cycles
0: ECC logic is disabled and reset (default after reset),
1: ECC logic is enabled.
00: 8 bits
01: 16 bits (default after reset). This value is mandatory for PC Cards.
10: reserved, do not use
11: reserved, do not use
0: PC Card, CompactFlash, CF+ or PCMCIA
1: NAND Flash (default after reset)
DocID018909 Rev 11
Flexible memory controller (FMC)
9 8 7 6 5 4
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3 2 1 0
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