STMicroelectronics STM32F405 Reference Manual page 1708

Revision history
Date
19-Oct-2012
1708/1731
Table 310. Document revision history (continued)
Version
SDIO:
Updated value and description for bits [45:40] and [7:1] in
R4 response. Updated value at bits [45:40] in
response.
CAN:
Updated Figure 335: Dual CAN block
Modified definition of CAN2SB bits in
register (CAN_FMR).
Added register access in
ETHERNET:
Updated standard for precision networked clock synchronization in
Section 33.1: Ethernet introduction
features.
Updated CR bit definition in
register (ETH_MACMIIAR).
Replace RTPR by PM bit in
USB OTG FS
2
Updated remote wakeup signaling bit and the resume
(continued)
interrupt in
Added peripheral register access in
and status
Updated INEPTXSA description in OTG_FS_DIEPTXFx.
Changed PHYSEL from bit 7 to bit 6 of the OTG_FS_GUSBCFG
register.
USB OTG HS
Updated remote wakeup signaling bit and the resume
interrupt in
Added peripheral register access in
and status
Updated OTG_HS_CID reset value.
Updated INEPTXSA description in OTG_HS_DIEPTXFx.
Updated FSLSPCS for LS host mode, added PHYSEL in
OTG_HS host configuration register
Renamed PHYSEL into PHSEL and changed from bit 7 to bit 6 of
the OTG_HS_GUSBCFG register.
Updated OTG_HS_DIEPEACHMSK1 and
OTG_HS_DOEPEACHMSK1 reset values.
DocID018909 Rev 11
Changes
Section 32.9: CAN registers
Section : Ethernet MAC MII address
Table 191: Source address
Section : Suspended state.
registerss.
Section : Suspended state.
registers.
Table 175:
Table 177: R5
diagram.
Section : CAN filter master
and Section 33.2.1: MAC core
filtering.
Section 34.16: OTG_FS control
Section 35.12: OTG_HS control
Section :
(OTG_HS_HCFG).
RM0090