STMicroelectronics STM32F405 Reference Manual page 1720

Revision history
Date
14-Oct-2014
1720/1731
Table 310. Document revision history (continued)
Version
FMC:
Modified step 7 in
Modified SDRAM refresh rate equations and example in
SDRAM Refresh Timer register (FMC_SDRTR)
8 definition of COUNT bits.
(continued)
Updated EXTMOD definition in
select control registers 1..4
Updated ADDSET definition in
select timing registers 1..4 (FMC_BTR1..4)
SRAM/NOR-Flash write timing registers 1..4
DocID018909 Rev 11
Changes
Section : SDRAM initialization.
Section : SRAM/NOR-Flash chip-
(FMC_BCR1..4).
Section : SRAM/NOR-Flash chip-
RM0090
Section :
and updated
and Section :
(FMC_BWTR1..4).