STMicroelectronics STM32F405 Reference Manual page 1427

RM0090
OTG_HS host channel-x interrupt register (OTG_HS_HCINTx) (x = 0..11, where
x = Channel_number)
Address offset: 0x508 + (Channel_number × 0x20)
Reset value: 0x0000 0000
This register indicates the status of a channel with respect to USB- and AHB-related events.
It is shown in
interrupt bit in the Core interrupt register (HCINT bit in OTG_HS_GINTSTS) is set. Before
the application can read this register, it must first read the host all channels interrupt
(OTG_HS_HAINT) register to get the exact channel number for the host channel-x interrupt
register. The application must clear the appropriate bit in this register to clear the
corresponding bits in the OTG_HS_HAINT and OTG_HS_GINTSTS registers.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 DTERR: Data toggle error
Bit 9 FRMOR: Frame overrun
Bit 8 BBERR: Babble error
Bit 7 TXERR: Transaction error
Indicates one of the following errors occurred on the USB.
Bit 6 NYET: Response received interrupt
Bit 5 ACK: ACK response received/transmitted interrupt
Bit 4 NAK: NAK response received interrupt
Bit 3 STALL: STALL response received interrupt
Bit 2 AHBERR: AHB error
Bit 1 CHH: Channel halted
Indicates the transfer completed abnormally either because of any USB transaction error or in
response to disable request by the application.
Bit 0 XFRC: Transfer completed
Transfer completed normally without any errors.
Figure 412. The application must read this register when the host channels
Reserved
CRC check failure
Timeout
Bit stuff error
False EOP
This error is generated only in Internal DMA mode when an AHB error occurs during an AHB
read/write operation. The application can read the corresponding DMA channel address
register to get the error address.
DocID018909 Rev 11
USB on-the-go high-speed (OTG_HS)
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