STMicroelectronics STM32F405 Reference Manual page 1299

RM0090
OTG_FS device V
Address offset: 0x0828
Reset value:
This register specifies the V
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 VBUSDT: Device V
OTG_FS device V
Address offset: 0x082C
Reset value: 0x0000 05B8
This register specifies the V
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DVBUSP: Device V
Specifies the V
OTG_FS device IN endpoint FIFO empty interrupt mask register:
(OTG_FS_DIEPEMPMSK)
Address offset: 0x834
Reset value: 0x0000 0000
This register is used to control the IN endpoint FIFO empty interrupt generation
(TXFE_OTG_FS_DIEPINTx).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
discharge time register (OTG_FS_DVBUSDIS)
BUS
0x0000 17D7
BUS
Reserved
discharge time
BUS
Specifies the V discharge time after V
BUS
V discharge time in PHY clocks / 1 024
BUS
Depending on your V
BUS
pulsing time register (OTG_FS_DVBUSPULSE)
BUS
BUS
Reserved
pulsing time
BUS
pulsing time during SRP. This value equals:
BUS
V pulsing time in PHY clocks / 1 024
BUS
Reserved
DocID018909 Rev 11
discharge time after V
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
pulsing during SRP. This value equals:
BUS
load, this value may need adjusting.
pulsing time during SRP.
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
USB on-the-go full-speed (OTG_FS)
pulsing during SRP.
BUS
9 8 7 6 5
VBUSDT
9 8 7 6 5
DVBUSP
rw rw rw rw rw rw rw rw rw rw rw rw
9 8 7 6 5
INEPTXFEM
4 3 2 1 0
4 3 2 1 0
4 3 2 1 0
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