STMicroelectronics STM32F405 Reference Manual page 1195

RM0090
Bits 9:8 RFFL: Rx FIFO fill level
Bit 7 Reserved, must be kept at reset value.
Bits 6:5 RFRCS: Rx FIFO read controller status
Bit 4 RFWRA: Rx FIFO write controller active
Bit 3 Reserved, must be kept at reset value.
Bits 2:1 MSFRWCS: MAC small FIFO read / write controllers status
Bit 0 MMRPEA: MAC MII receive protocol engine active
Ethernet (ETH): media access control (MAC) with DMA controller
This gives the status of the Rx FIFO fill-level:
00: RxFIFO empty
01: RxFIFO fill-level below flow-control de-activate threshold
10: RxFIFO fill-level above flow-control activate threshold
11: RxFIFO full
It gives the state of the Rx FIFO read controller:
00: IDLE state
01: Reading frame data
10: Reading frame status (or time-stamp)
11: Flushing the frame data and status
When high, it indicates that the Rx FIFO write controller is active and transferring a received
frame to the FIFO.
When high, these bits indicate the respective active state of the small FIFO read and write
controllers of the MAC receive frame controller module.
When high, it indicates that the MAC MII receive protocol engine is actively receiving data
and is not in the Idle state.
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