STMicroelectronics STM32F405 Reference Manual page 1719

RM0090
Date
14-Oct-2014
Table 310. Document revision history (continued)
Version
Memory and bus architecture:
Updated Table 3: Memory mapping vs. Boot mode/physical remap
in STM32F405xx/07xx and STM32F415xx/17xx
Memory mapping vs. Boot mode/physical remap in STM32F42xxx
and STM32F43xxx.
RCC (STM32F40/41xx) and RCC (STM32F42/43xx):
Removed all references to Flash programming manual. Changed
RCC_AHB1LPENR, RCC_APB1LPENR, RCC_APB2LPENR,
RCC_PLLI2SCFGR and RCC_APB2LPENR reset values.
Updated access type to "r" for bits 24 to 31 in RCC_CSR.
GPIOs:
Updated Figure 27: Selecting an alternate function on STM32F42xxx
and STM32F43xxx.
IWDG
Update note in
(LSI).
CRYPTO and HASH
Removed STM32F405/407xx and STM32F42xx from the whole
sections.
8
Removed STM32F405/407xx and STM32F42xx from the whole
section.
TIM10/11/13/14
Added TIMx_DIER description in
registers.
ETHERNET:
Updated Table 186: Clock
USB OTG FS:
Removed TRDT formula in
time and added
USB OTG HS:
Removed TRDT formula in
time and added
FSMC:
Updated EXTMOD definition in
select control registers 1..4
Updated ADDSET definition in
select timing registers 1..4 (FSMC_BTR1..4)
SRAM/NOR-Flash write timing registers 1..4
DocID018909 Rev 11
Changes
Table 106: Min/max IWDG timeout period at 32 kHz
Section 19.5: TIM10/11/13/14
range.
Section 34.17.7: Worst case response
Table 200: TRDT values.
Section 35.13.8: Worst case response
Table 208: TRDT values.
Section : SRAM/NOR-Flash chip-
(FSMC_BCR1..4).
Section : SRAM/NOR-Flash chip-
Revision history
and Table 4:
and Section :
(FSMC_BWTR1..4).
1719/1731
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