STMicroelectronics STM32F405 Reference Manual page 1711

RM0090
Date
19-Feb-2013
Table 310. Document revision history (continued)
Version
Updated Section 2: Memory and bus
Updated Figure 1: System architecture for STM32F405xx/07xx and
STM32F415xx/17xx
STM32F405xx/07xx and STM32F415xx/17xx
Table 4: Memory mapping vs. Boot mode/physical
Figure 5: Sequential 32-bit instruction
from Table 12: Program/erase
PWR:
Updated Figure 7: Power supply
Updated Section 5.1.3: Voltage
Added ADCDC1 bit in
(PWR_CR) for STM32F42xxx and
SYSCFG:
Added ADCxDC2 bit in
configuration register (SYSCFG_PMC) for STM32F42xxx and
STM32F43xxx.
4
ADC:
Updated Section 13.9.3: Interleaved
trigger mode, and
simultaneous mode
Updated Section : Temperature sensor, VREFINT and VBAT internal
channels, Section 13.10: Temperature
Battery charge
RTC:
Updated BKP[31:0] bit description in
registers (RTC_BKPxR).
I2C:
Updated Section 27.3.5: Programmable noise
DocID018909 Rev 11
Changes
architecture.
devices, and Figure 1: System architecture for
execution. removed note 1
parallelism.
overview.
regulator.
Section 5.5.1: PWR power control register
STM32F43xxx.
Section 8.2.3: SYSCFG peripheral mode
mode,
Section 13.9.5: Combined regular/injected
to describe case of interrupted conversion.
sensor, and
monitoring.
Section 26.6.20: RTC backup
Revision history
devices. Updated
remap. Updated
Section 13.9.4: Alternate
Section 13.11:
filter.
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