STMicroelectronics STM32F405 Reference Manual page 1647

RM0090
Bits 15:8 ATTWAIT[7:0]: Attribute memory x wait time
Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, NOE),
for PC Card/NAND Flash read or write access to attribute memory space on socket x. The
duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the
end of the programmed value of HCLK:
Bits 7:0 ATTSET[7:0]: Attribute memory x setup time
Defines the number of HCLK (+1) clock cycles to set up address before the command
assertion (NWE, NOE), for PC CARD/NAND Flash read or write access to attribute memory
space on socket x:
I/O space timing register 4 (FMC_PIO4)
Address offset: 0xB0
Reset value: 0xFCFCFCFC
The FMC_PIO4 read/write registers contain the timing information used to access the I/O
space of the 16-bit PC Card/CompactFlash.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IOHIZ[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:24 IOHIZ[7:0]: I/O x data bus Hi-Z time
Defines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the
start of a PC Card write access to I/O space on socket x. Only valid for write transaction:
0000 0000: reserved
0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
1111 1110: 255 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT)
1111 1111: Reserved
0000 0000: 1 HCLK cycle
1111 1110: 255 HCLK cycles
1111 1111: Reserved
IOHOLD[7:0]
0000 0000: 0 HCLK cycle
1111 1111: 255 HCLK cycles
DocID018909 Rev 11
Flexible memory controller (FMC)
9 8 7
IOWAIT[7:0]
6 5 4 3 2 1 0
IOSET[7:0]
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