STMicroelectronics STM32F405 Reference Manual page 1712

Revision history
Date
19-Feb-2013
1712/1731
Table 310. Document revision history (continued)
Version
FSMC:
Updated write FIFO size in
Updated Figure 432: FSMC block
Updated Section 36.5.4: NOR Flash/PSRAM controller
asynchronous
Modified differences between Mode B and mode 1 in
2/B - NOR
Modified differences between Mode C and mode 1 in
C - NOR Flash - OE
Modified differences between Mode D and mode 1 in
D - asynchronous access with extended
4
Updated NWAIT signal in
(continued)
read access,
Figure 449: Wait
multiplexed read mode - NOR, PSRAM
Synchronous multiplexed write mode - PSRAM
Updated Table 195
Updated Section : SRAM/NOR-Flash chip-select control registers
1..4 (FSMC_BCR1..4).
DEBUG
Updated Figure 483: Block diagram of STM32 MCU and Cortex®-
M4 with FPU-level debug
DocID018909 Rev 11
Changes
Section 36.1: FSMC main
diagram.
transactions.
Flash.
toggling.
Figure 447: Asynchronous wait during a
Figure 448: Asynchronous wait during a write
configurations, Figure 450: Synchronous
to Table 214.
support.
RM0090
features.
Section : Mode
Section : Mode
Section : Mode
address.
access,
(CRAM), and Figure 451:
(CRAM).